//-----------------------------------------------
//	module name: bidirDelay4U
//	author: Anping HE (heap@lzu.edu.cn)
//	version: 1st version (2021-11-05)
//	description: 
//		1. bidirected delay, e.g., equal delays for both req from left to right and ack from right to left
//		2. 4U for 4 bidirected delay units
//-----------------------------------------------

`timescale 1ns / 1ps

module bidirDelay10U(inR, inA, outR, outA);

input   inR, outA;

output  outR, inA; 

wire w_req_0, w_ack_0; 
wire w_req_1, w_ack_1; 
wire w_req_2, w_ack_2; 
wire w_req_3, w_ack_3; 
wire w_req_4, w_ack_4; 
wire w_req_5, w_ack_5; 
wire w_req_6, w_ack_6; 
wire w_req_7, w_ack_7; 
wire w_req_8, w_ack_8; 
wire w_req_9, w_ack_9; 

bidirDelay2U delay(inR, inA, w_req_0, w_ack_0);
bidirDelay2U delay0(w_req_0, w_ack_0, w_req_1, w_ack_1); 
bidirDelay2U delay1(w_req_1, w_ack_1, w_req_2, w_ack_2); 
bidirDelay2U delay2(w_req_2, w_ack_2, w_req_3, w_ack_3); 
bidirDelay2U delay3(w_req_3, w_ack_3, w_req_4, w_ack_4); 
bidirDelay2U delay4(w_req_4, w_ack_4, w_req_5, w_ack_5); 
bidirDelay2U delay5(w_req_5, w_ack_5, w_req_6, w_ack_6); 
bidirDelay2U delay6(w_req_6, w_ack_6, w_req_7, w_ack_7); 
bidirDelay2U delay7(w_req_7, w_ack_7, w_req_8, w_ack_8); 
bidirDelay2U delay8(w_req_8, w_ack_8, w_req_9, w_ack_9); 
bidirDelay2U delay9(w_req_9, w_ack_9, outR, outA); 

endmodule
